1. Field Of The Invention
This invention relates to computer systems and, more particularly, to methods and apparatus for providing an improved programmable priority interrupt controller for use with modern operating systems.
2. History Of The Prior Art
Historically, computers utilizing microprocessors manufactured by Intel Corporation of Santa Clara, Calif., such as the 8088, 8086, 80186, 80286, i386.TM., and i486.TM. microprocessors (herein referred to as the Intel processors) have used an Intel 8259 programmable interrupt controller (PIC) or an interrupt controller patterned thereon. This interrupt controller provides interrupt signals to an associated processor in response to interrupt signals generated by various hardware devices associated with the processor. The priority level of an interrupt provided by a PIC controller is fixed for each associated hardware device and depends upon the input pin position on the PIC controller at which the interrupt signal is received. That is, an interrupt from the keyboard is always connected to the PIC at the same input pin position and is always transferred to the processor by the interrupt controller at a certain priority level, while an interrupt from another hardware device is always connected to the PIC at a different input pin position and is always transferred to the processor by the controller at another priority level. Thus, these priority levels are hardwired and remain constant throughout the operation of the device. In systems using a plurality of processors, such an interrupt controller is capable of furnishing interrupts to only a single one of the processors. Consequently, it has been necessary to provide software solutions to control the inter-relation of interrupts in systems using many processors.
With more advanced computers running advanced operating systems, it is desirable to be able to change the priority level at which interrupt signals from a particular hardware component are handled as the circumstances of operation change. That is, a particular hardware device may be very important in certain instances (such as when a computer system operates as a server) and less important in other circumstances (where a computer operates as a desktop computer). Therefore, it is desirable that the priority levels of particular hardware be programmable within any particular computer.
Moreover, the efficient operation of a computer system depends on the correct interrelation between the operation of the hardware and the software. Consequently, the priority levels of interrupts associated with software processes (tasks) and of interrupts from hardware devices should be coordinated and made programmable. In this way, the use of interrupts may be made to depend on the circumstances of the computer system operation taking place. More advanced operating systems provide for this coordination of hardware and task interrupt priority levels.
Recently, a new interrupt controller has been designed for use with Intel processors which is capable of accomplishing these desirable features, among others. Intel Corporation markets this interrupt controller as the 82489DX Advanced Programmable Interrupt Controller (APIC). This controller provides multiprocessor interrupt management which includes facilities for transferring interrupts between processors and to the least used one of a plurality of processors used in a multiprocessor system. This controller also provides programmable interrupts for both tasks and devices and manages their inter-relation. Such a controller is described in detail in a publication entitled 82489DX Advanced Programmable Interrupt Controller, published by Intel Corporation of Santa Clara, Calif.
Even though the APIC controller is a relatively new system component, it was designed at a time before it was expected that more modern operating systems would find extensive use with the Intel processors. When the APIC controller was designed, it was expected that only sixteen interrupt priority levels would be required for any of these microprocessors. Since that time, new operating systems have been written to be used with the Intel processors. Similarly, older operating systems which utilize thirty-two levels of interrupt priority have been modified so that they may be more easily used with the Intel processors. For example, the Microsoft Windows NT Operating System utilizes thirty-two levels of priority in assigning interrupts and is expected to find wider use in systems utilizing Intel processors. In order to handle these modern operating systems, software processes must be utilized to provide the necessary levels of interrupts for the Intel processors using the APIC controllers. Such software methods cause a substantial decrease in the operating speed of such systems thereby creating the possibility of loss of data.
Additionally, the APIC allows priority to be programmable by assigning a vector to each input pin. This vector is written into and maintained in a register in the APIC controller associated with an input pin at which an interrupt may appear. The vector includes a number of bits which designate the priority of the interrupt and the address in an interrupt vector table in memory of the handler process for the interrupt. The assignment of bits in the vector is such that all of the possible levels of priorities which may be assigned to any device or task are widely separated in memory rather than being associated in adjacent entries. This substantially increases the spread of the entries used in the interrupt vector table. This increase in spread interferes with entries which has been previously used by many application programs for other purposes and therefore tends to make these older application programs incompatible with the newer hardware.